The role of tunnel barriers in phase-state low electron-number drive transistors (PLEDTRs)

IEEE Transactions on Electron Devices

Volumn 48, Issue 6, 2001, Pages 1103-1108

  Mizuta, H ^a   Wagner, M ^a   Nakazato, K ^a  

^a HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

Author keywords

Semiconductor device modeling; Semiconductor memories; Tunnel transistors; Tunneling

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON TUNNELING; NUMERICAL ANALYSIS; SEMICONDUCTOR DEVICE MODELS; SIGNAL TO NOISE RATIO;

PHASE-STATE LOW ELECTRON-NUMBER DRIVE TRANSISTORS (PLEDTR);

TRANSISTORS;

EID: 0035367063     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.925234     Document Type: Article

References (14)

1. PLED - Planar localized electron devices
2. Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cells
3. Normally-off PLED (Planar Localized Electron Device) for nonvolatile memory
4. Phase-state low electron-number drive memory (PLEDM); A high-speed and high-density random access memory
5. Silicon stacked transistor with source and drain tunnel barriers
6. Scaling theory for double-gate SOI MOSFET's
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8. Tunneling in a finite superlattice
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12. Theoretical study of deep-trap-assisted anomalous currents in worst-bit cells of dynamic random-access memories (DRAM's)
13. New ultra-fast switching mechanism in semiconductor heterostructures