Compact analytical modeling of SOI partially depleted MOSFETs with LETISOI

Solid-State Electronics

Volumn 45, Issue 4, 2001, Pages 599-605

  Faynot, O ^a   Poiroux, T ^a   Pelloie, J L ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; COMPUTER SIMULATION; INTERFACES (MATERIALS); MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; TRANSIENTS; ULSI CIRCUITS;

BODY-CONTACTED DEVICES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0035334184     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(01)00083-1     Document Type: Article

References (12)

1. Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit perfomance
2. BSIM4 gate leakage model including source-drain partition
3. Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques
4. History dependence of non-fully depleted (NFD) digital SOI circuits