A single-electron shut-off transistor for a scalable sub-0.1-μm memory

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 301-304

  Osabe, T ^a   Ishii, T ^a   Mine, T ^a   Murai, F ^a   Yano, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COULOMB BLOCKADE; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON TRAPS; LEAKAGE CURRENTS; POLYSILICON; ULTRATHIN FILMS;

SINGLE ELCTRON SHUT OFF (SESO) TRANSISTORS;

TRANSISTORS;

EID: 0034453423     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. TITE RAM: A new SOI DRAM gain cell for Mbit DRAM's
2. An experimental high density DRAM cell with a built-in gain stage
3. A complementary gain cell technology for sub-1V supply DRAMs
4. A surrounding gate transistor (SGT) gain cell for ultra high density DRAMs
5. A self-amplifying (SEA) cell for future high density DRAMs
6. Silicon stacked tunnel transistor for high speed and high-density random access memory gain cells
7. Single-electron memory for giga-to-tera bit storage