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Volumn E79-C, Issue 4, 1996, Pages 530-536

A 2. 6-ns 64-b fast and small CMOS adder

Author keywords

Addition; Binary look ahead adder; Carry look ahead adder; Carry select; CMOS; Modified carry select; VLSI

Indexed keywords

CARRY LOGIC; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; VLSI CIRCUITS;

EID: 0030124812     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (6)

References (10)
  • 7
    • 85027102422 scopus 로고    scopus 로고
    • 2. 4-ns, 16-b, 0. 5-μm CMOS arithmetic logic unit for microprogrammable video signal processor LSIs," CICC Proc. , pp. 12. 4. 1-12. 4. 4, 1993.
    • K. Suzuki, M. Yamashita, J. Goto, T. Inoue, Y. Koseki et al, "A 2. 4-ns, 16-b, 0. 5-μm CMOS arithmetic logic unit for microprogrammable video signal processor LSIs," CICC Proc. , pp. 12. 4. 1-12. 4. 4, 1993.
    • M. Yamashita, J. Goto, T. Inoue, Y. Koseki Et Al, "A
    • Suzuki, K.1
  • 8
    • 0024131555 scopus 로고    scopus 로고
    • 3. 1 ns 32 b CMOS adder in multiple output domino logic," ISSCC Digest of Technical Papers, pp. 140-141, Feb. 1988.
    • I. S. Hwang and A. L. Fisher, "A 3. 1 ns 32 b CMOS adder in multiple output domino logic," ISSCC Digest of Technical Papers, pp. 140-141, Feb. 1988.
    • "A
    • Hwang, I.S.1    Fisher, A.L.2
  • 9
    • 85060884542 scopus 로고    scopus 로고
    • 1. 5ns 32 b CMOS ALU in double passtransistor logic," ISSCC Digest of Technical Papers, pp. 90-91, Feb. 1993.
    • M. Suzuki, N. Ohkubo, T. Yamanaka, A. Shimizu, and K. Sasaki, "A 1. 5ns 32 b CMOS ALU in double passtransistor logic," ISSCC Digest of Technical Papers, pp. 90-91, Feb. 1993.
    • N. Ohkubo, T. Yamanaka, A. Shimizu, and K. Sasaki, "A
    • Suzuki, M.1
  • 10
    • 0029487720 scopus 로고    scopus 로고
    • 0. 4 μm 1. 4 ns 32 b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique," Symposium on VLSI Circuit, pp. 9-10, 1995.
    • A. Inoue, Y. Kawabeet al, "A 0. 4 μm 1. 4 ns 32 b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique," Symposium on VLSI Circuit, pp. 9-10, 1995.
    • Y. Kawabeet Al, "A
    • Inoue, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.