Partitioning sequential circuits on dynamically reconfigurable FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1998, Pages 161-167

  Chang, Douglas ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTATIONAL METHODS; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

DYNAMICALLY RECONFIGURABLE FIELD PROGRAMMABLE GATE ARRAYS (DRFPGA); FORCE DIRECTED SCHEDULING (FDS) ALGORITHMS; PARTITION SEQUENTIAL CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0031628363     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)