Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1996, Pages 459-462

  Kotaki, H ^a   Kakimoto, S ^a   Nakano, M ^a   Matsuoka, T ^a   Adachi, K ^a   Sugimoto, K ^a   Fukushima, T ^a   Sato, Y ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); ION IMPLANTATION; POLISHING; SEMICONDUCTING FILMS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; VOLTAGE CONTROL;

ADVANCED ISOLATION; BULK DYNAMIC THRESHOLD VOLTAGE MOSFET; GATE TO SHALLOW WELL CONTACT; PROPAGATION DELAY TIME; SILIDATION; ULTRA LOW POWER DUAL GATE CMOS;

MOSFET DEVICES;

EID: 0030386822     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)