Modeled and measured instruction fetching performance for superscalar microprocessors

IEEE Transactions on Parallel and Distributed Systems

Volumn 9, Issue 6, 1998, Pages 570-578

  Wallace, Steven ^a,b   Bagherzadeh, Nader ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IEEE   (United States)

Author keywords

Branch target buffer; Computer architecture; Instruction fetching; Performance analysis; Superscalar microprocessor

Indexed keywords

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; MICROPROGRAMMING; PARALLEL ALGORITHMS;

BRANCH TARGET BUFFER; INSTRUCTION FETCHING; SUPERSCALAR MICROPROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 0032095834     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.689444     Document Type: Article

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