-
1
-
-
33747642185
-
-
35, pp. 1147-1180, Oct. 1988.
-
L.O. Chua and L. Yang, " Cellular neural networks: Theory and applications," IEEE Trans. Circuit Syst., vol. 35, pp. 1147-1180, Oct. 1988.
-
And L. Yang, " Cellular Neural Networks: Theory and Applications," IEEE Trans. Circuit Syst., Vol.
-
-
Chua, L.O.1
-
2
-
-
0031188728
-
-
0.8-/j,m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage," IEEE J. Solid-State Circuits, vol. 32, pp. 1013-1026, July 1997.
-
R. Domfnguez-Castro,S. Espejo, A. Rodriguez-Vâzquez, R. A. Carmona, P. Földesy, A. Zarand y, P. Szolgay, T. Szirânyi, and T. Roska, " A 0.8-/j,m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage," IEEE J. Solid-State Circuits, vol. 32, pp. 1013-1026, July 1997.
-
Espejo, A. Rodriguez-Vâzquez, R. A. Carmona, P. Földesy, A. Zarand Y, P. Szolgay, T. Szirânyi, and T. Roska, " A
-
-
Domfnguez-Castro, R.1
-
3
-
-
0032025848
-
-
16 X 16 cellular neural network universal chip: The first complete single-chip dynamic computer array with distributed memory and with gray-scale input-output," Analog Integr. Circuits Signal Processing, vol. 15, no. 3, pp. 3-14, 1998.
-
J.M. Cruzand L. O. Chua, " A 16 X 16 cellular neural network universal chip: The first complete single-chip dynamic computer array with distributed memory and with gray-scale input-output," Analog Integr. Circuits Signal Processing, vol. 15, no. 3, pp. 3-14, 1998.
-
L. O. Chua, " A
-
-
Cruzand, J.M.1
-
4
-
-
0030735279
-
-
44, pp. 12-20, Mar. 1997.
-
E.Y. Chou, B. J. Sheu, and R. C. Chang, " VLSI design of optimization and image processing cellular neural networks," IEEE Trans. Circuits Syst.-I, vol. 44, pp. 12-20, Mar. 1997.
-
B. J. Sheu, and R. C. Chang, " VLSI Design of Optimization and Image Processing Cellular Neural Networks," IEEE Trans. Circuits Syst.-I, Vol.
-
-
Chou, E.Y.1
-
5
-
-
0029267772
-
-
30, pp. 235-243, Mar. 1995.
-
P. Kinget and J. Steyaert, " A programmable analog cellular neural network CMOS chip for high speed," IEEE J. Solid-State Circuits, vol. 30, pp. 235-243, Mar. 1995.
-
And J. Steyaert, " A Programmable Analog Cellular Neural Network CMOS Chip for High Speed," IEEE J. Solid-State Circuits, Vol.
-
-
Kinget, P.1
-
6
-
-
0031075969
-
-
44,pp. 149-152, Feb. 1997.
-
M. Anguita,F. J. Pelayo, F. J. Fernand ez, and A. Prieto, " A low-power CMOS implementation of programmable CNNs with embedded photosensors," lEEETrans. CircuitsSyst.-I,vol44,pp. 149-152, Feb. 1997.
-
F. J. Pelayo, F. J. Fernand Ez, and A. Prieto, " A Low-power CMOS Implementation of Programmable CNNs with Embedded Photosensors," LEEETrans. CircuitsSyst.-I,vol
-
-
Anguita, M.1
-
7
-
-
0032028644
-
-
6 X 6 cells interconnectionoriented programmable chip for CNN," Analog Integr. Circuits Signal Processing, vol. 15, no. 3, pp. 15-26, 1998.
-
M. Salerno,F. Sargeni, and V. Bonaiuto, " A 6 X 6 cells interconnectionoriented programmable chip for CNN," Analog Integr. Circuits Signal Processing, vol. 15, no. 3, pp. 15-26, 1998.
-
F. Sargeni, and V. Bonaiuto, " A
-
-
Salerno, M.1
-
8
-
-
0027554307
-
-
40, pp. 206-215, Mar. 1993.
-
G.F. Dalla Betta, S. Graffi, Zs. M. Kovâcs, and G. Masetti, " CMOS implementation of an analogically programmable cellular neural network," IEEE Trans. Circuits Syst.-II, vol. 40, pp. 206-215, Mar. 1993.
-
Betta, S. Graffi, Zs. M. Kovâcs, and G. Masetti, " CMOS Implementation of An Analogically Programmable Cellular Neural Network," IEEE Trans. Circuits Syst.-II, Vol.
-
-
Dalla, G.F.1
-
9
-
-
0030729879
-
-
16 by 16 cellular neural network implementation," Analog Integr. Circuits Signal Processing, vol. 12, no. 3, pp. 59-70, 1998.
-
A. Paasio,A. Dawidziuk, K. Halonen, and V. Porra, " Fast and compact 16 by 16 cellular neural network implementation," Analog Integr. Circuits Signal Processing, vol. 12, no. 3, pp. 59-70, 1998.
-
A. Dawidziuk, K. Halonen, and V. Porra, " Fast and Compact
-
-
Paasio, A.1
-
10
-
-
0028483910
-
-
28, pp. 895-905, Aug. 1994.
-
S. Espejo,A. Rodriguez-Vâzquez, R. Dommguez-Castro, J. L. Huertas, and E. Sânchez-Sinencio , " Smart-pixel cellular neural networks in analog current-mode CMOS technology," IEEE J. Solid-State Circuits, vol. 28, pp. 895-905, Aug. 1994.
-
A. Rodriguez-Vâzquez, R. Dommguez-Castro, J. L. Huertas, and E. Sânchez-Sinencio , " Smart-pixel Cellular Neural Networks in Analog Current-mode CMOS Technology," IEEE J. Solid-State Circuits, Vol.
-
-
Espejo, S.1
-
11
-
-
0032155149
-
-
45, pp. 968-973, Sept. 1998.
-
M. Anguita,F. J. Pelayo, F. J. Fernand ez, and A. Prieto, " Area efficient implementations of fixed-template CNNs," IEEE Trans. Circuits Syst.-I, vol. 45, pp. 968-973, Sept. 1998.
-
F. J. Pelayo, F. J. Fernand Ez, and A. Prieto, " Area Efficient Implementations of Fixed-template CNNs," IEEE Trans. Circuits Syst.-I, Vol.
-
-
Anguita, M.1
-
12
-
-
0027561012
-
-
40, pp. 147-156, Mar. 1993.
-
J.E. Varrientos, E. Sânchez-Sinencio, and J. Ramfrez-Angulo, " A current-mode cellular neural networks implementation," IEEE Trans. Circuits Syst.-II, vol. 40, pp. 147-156, Mar. 1993.
-
E. Sânchez-Sinencio, and J. Ramfrez-Angulo, " A Current-mode Cellular Neural Networks Implementation," IEEE Trans. Circuits Syst.-II, Vol.
-
-
Varrientos, J.E.1
-
15
-
-
0029358619
-
-
2-dimensional silicon retina," IEEEJ. Solid-State Circuits, vol. 30, pp. 890-897, Aug. 1995.
-
_, " A new structure of the 2-dimensional silicon retina," IEEEJ. Solid-State Circuits, vol. 30, pp. 890-897, Aug. 1995.
-
A New Structure of the
-
-
-
16
-
-
0033078984
-
-
2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector," IEEE J. Solid-State Circuits, vol. 34, pp. 241-247, Feb. 1999.
-
H.C. Jiang and C. Y. Wu, " A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector," IEEE J. Solid-State Circuits, vol. 34, pp. 241-247, Feb. 1999.
-
And C. Y. Wu, " A
-
-
Jiang, H.C.1
-
17
-
-
0032265330
-
-
3, Sept. 1998, pp. 277-270.
-
C. Y Wu and W. C. Yen, " The neuron-bipolar junction transistor (fBJT)-a new device structure for VLSI neural network implementation," in Proc. Int. Conf. Electronics, Circuits and Systems, vol. 3, Sept. 1998, pp. 277-270.
-
And W. C. Yen, " The Neuron-bipolar Junction Transistor (FBJT)-a New Device Structure for VLSI Neural Network Implementation," in Proc. Int. Conf. Electronics, Circuits and Systems, Vol.
-
-
Wu, C.Y.1
-
18
-
-
0032662197
-
-
4, June 1999, pp. 505-508.
-
W.C. Yen and C. Y Wu, " A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level," in Proc. IEEE Int. Symp. Circuits Systems, vol. 4, June 1999, pp. 505-508.
-
And C. Y Wu, " A New Compact Neuron-bipolar Cellular Neural Network Structure with Adjustable Neighborhood Layers and High Integration Level," in Proc. IEEE Int. Symp. Circuits Systems, Vol.
-
-
Yen, W.C.1
-
19
-
-
27644460436
-
-
2, Sept. 1999, pp. 713-716.
-
_, " A new compact programmable t>BJT cellular neural network structure with adjustable neighborhood layers for image processing," in Proc. Int. Conf. Electronics, Circuits and Systems, vol. 2, Sept. 1999, pp. 713-716.
-
A New Compact Programmable T>BJT Cellular Neural Network Structure with Adjustable Neighborhood Layers for Image Processing," in Proc. Int. Conf. Electronics, Circuits and Systems, Vol.
-
-
-
20
-
-
0027578080
-
-
40, pp. 147-156, Apr. 1993.
-
K. R. Crounse, T. Roska, and L. O. Chua, " Image halftoning with cellular neural networks," IEEE Trans. Circuits Syst.-II, vol. 40, pp. 147-156, Apr. 1993.
-
T. Roska, and L. O. Chua, " Image Halftoning with Cellular Neural Networks," IEEE Trans. Circuits Syst.-II, Vol.
-
-
Crounse, K.R.1
-
21
-
-
0027562138
-
-
40, pp. 1822-1895, Mar. 1993.
-
T. Roska,J. Harnori, E. Labos, K. Lotz, L. Orzö, J. Takâcs, P. L. Venetianer, Z. Vidnyânsky, and A. Zarândy, " The use of CNN model in the subcortical visual pathway," IEEE Trans. Circuits Syst.-I, vol. 40, pp. 1822-1895, Mar. 1993.
-
Harnori, E. Labos, K. Lotz, L. Orzö, J. Takâcs, P. L. Venetianer, Z. Vidnyânsky, and A. Zarândy, " The Use of CNN Model in the Subcortical Visual Pathway," IEEE Trans. Circuits Syst.-I, Vol.
-
-
Roska, T.1
-
23
-
-
14344268558
-
-
26, pp. 551-566, Nov./Dec. 1998.
-
L. Kék and A. Zarândy, " Implementation of large-neighborhood nonlinear templates on the CNN universal machine," Int. J. Circuit Theory Appi, vol. 26, pp. 551-566, Nov./Dec. 1998.
-
And A. Zarândy, " Implementation of Large-neighborhood Nonlinear Templates on the CNN Universal Machine," Int. J. Circuit Theory Appi, Vol.
-
-
Kék, L.1
-
24
-
-
0031645087
-
-
5th IEEE Int. Workshop Cellular Networks and Their Applications, Apr. 1998, pp. 88-93.
-
M.H. ter Brugge, J. H. Stevens, J. A. G. Nijhuis, and L. Spaanenburg, " Efficient DTCNN implementations for large-neighborhood functions," in Proc. 5th IEEE Int. Workshop Cellular Networks and Their Applications, Apr. 1998, pp. 88-93.
-
Brugge, J. H. Stevens, J. A. G. Nijhuis, and L. Spaanenburg, " Efficient DTCNN Implementations for Large-neighborhood Functions," in Proc.
-
-
Ter, M.H.1
-
25
-
-
0027553986
-
-
40, pp. 163-173, Mar. 1993.
-
T. Roska and L. O. Chua, " The CNN universal machine: An analogic array computer," IEEE Trans. Circuits Syst.-II, vol. 40, pp. 163-173, Mar. 1993.
-
And L. O. Chua, " The CNN Universal Machine: An Analogic Array Computer," IEEE Trans. Circuits Syst.-II, Vol.
-
-
Roska, T.1
-
26
-
-
0018985618
-
-
27, pp. 414-419, Feb. 1980.
-
C. Y Wu and C. Y Wu, " An analysis and the fabrication technology of the LAMBDA bipolar transistor," IEEE Trans. Electron Devices, vol. ED-27, pp. 414-419, Feb. 1980.
-
And C. Y Wu, " An Analysis and the Fabrication Technology of the LAMBDA Bipolar Transistor," IEEE Trans. Electron Devices, Vol. ED
-
-
Wu, C.Y.1
-
27
-
-
0032649219
-
-
72, pp. 241-248, June 1999.
-
C. Y Wu and H. C. Jiang, " An improved BJT-based silicon retina with tunable image smoothing capability," IEEE Trans. VLSI Syst., vol. 72, pp. 241-248, June 1999.
-
And H. C. Jiang, " An Improved BJT-based Silicon Retina with Tunable Image Smoothing Capability," IEEE Trans. VLSI Syst., Vol.
-
-
Wu, C.Y.1
-
30
-
-
0033353986
-
-
23, pp. 281-290, NovVDec. 1999.
-
A. Paasio,A. Kananen, K. Halonen, and V. Porra, " A QCIF resolution binary I/O CNN-UM chip," J. VLSI Signal Processing, vol. 23, pp. 281-290, NovVDec. 1999.
-
A. Kananen, K. Halonen, and V. Porra, " A QCIF Resolution Binary I/O CNN-UM Chip," J. VLSI Signal Processing, Vol.
-
-
Paasio, A.1
|