A 2.5V 12b 54Msample/s 0.25μm CMOS ADC in 1mm2

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 132-133+439

  Van der Ploeg, H ^a   Hoogzaad, G ^a   Termeer, H A H ^a   Vertregt, M ^a   Roovers, R L J ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CALIBRATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; RESISTORS; SIGNAL PROCESSING;

DIGITAL RESIDUE SIGNAL PROCESSING; RESIDUE AMPLIFIERS;

CMOS INTEGRATED CIRCUITS;

EID: 0035058523     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 3.3V, 10-b, 25-MSample/s Two-Step ADC in 0.35μm CMOS
2. A 13b 40Msample/s CMOS pipelined folding ADC with background offset trimming
3. A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz
4. A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
5. A 14b 100Msample/s 3-stage A/D converter