A 13b 40MSample/s CMOS pipelined folding ADC with background offset trimming

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 36-37

  Choe, M J ^a   Song, B S ^a   Bacrania, K ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); FEEDBACK; LOGIC DESIGN; SAMPLED DATA CONTROL SYSTEMS;

PIPELINED FOLDING ANALOG TO DIGITAL CONVERTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 0034430967     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 12b, 60MSample/s cascaded folding and interpolation ADC
2. 2
3. A 13b 10MSample/s ADC digitally calibrated with oversampling Σδ converter
4. An 8b 100MSample/s CMOS pipelined folding ADC
5. 2