A process and technology-tolerant IDDQ method for IC diagnosis

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 145-150

  Patel, C ^a   Plusquellic, J ^a  

^a Baltimore County   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DEFECTS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; RELIABILITY;

DEEP SUBMICRON TECHNOLOGIES; QUIESCENT SIGNAL ANALYSIS; TRANSIENT SIGNAL ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0035020492     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. DDQ test: Sensitivity analysis of scaling
2. Current signatures
3. DDQ test
4. Current ratios: A self-scaling technique for production IDDQ testing
5. Defect detection using power supply transient signal analysis
6. Signature analysis for IC diagnosis and failure analysis
7. DDQ probabilistic signatures: Experimental results
8. SPACE, layout to circuit extraction software module of the nelsis IC design system