Mechanisms of the chemical mechanical polishing (CMP) process in integrated circuit fabrication

CIRP Annals - Manufacturing Technology

Volumn 50, Issue 1, 2001, Pages 233-238

  Saka, N ^a   Lai, J Y ^a   Chun, J H ^a   Suh, N P ^a  

^a Massachusetts Institute of Technology   (United States)

Author keywords

Chemical Mechanical Polishing; Integrated Circuits; Semiconductor Manufacturing

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; SILICON WAFERS; SURFACE ROUGHNESS; ULSI CIRCUITS;

DISHING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034960709     PISSN: 00078506     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0007-8506(07)62112-X     Document Type: Article

References (15)

1. Pattern geometry effects in the chemical-mechanical polishing of inlaid copper structures
2. Tantalum, copper and damascene: The future of Interconnects
3. Inlaid copper multilevel interconnections using plnanarization by chemical-mechanical polishing
4. Multilevel pattern effects in copper CMP, CMP symposium
5. Technological advances in fine abrasive processes
6. Pattern planarization model of chemical mechanical polishing
7. Electrical characterization of copper chemical mechanical polishing
8. Wear-Contact problems and modeling of chemical mechanical polishing
9. The theory and design of plate glass polishing machines
10. Modification of the preston equation for the chemical-mechanical polishing of copper
11. The effect of pad wear on the chemical mechanical polishing of silicon wafers