Symbolic functional and timing verification of transistor-level circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 526-530

  McDonald, Clayton B ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; DATA STRUCTURES; DECISION THEORY;

MULTITERMINAL BINARY DECISION DIAGRAMS; STATIC ANALYSIS; TRANSISTOR LEVEL CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0033356203     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)