-
1
-
-
0342400688
-
Commercial Design Verification: Methodology and Tools
-
C. Pixley, N.R. Strader, W.C. Bruce, J. Park, M. Kaufmann, K. Shultz, M. Burns, J. Kumar, J. Yuan, and J. Nguyen, "Commercial Design Verification: Methodology and Tools," Proc. Intl. Test Conf., 1997.
-
(1997)
Proc. Intl. Test Conf.
-
-
Pixley, C.1
Strader, N.R.2
Bruce, W.C.3
Park, J.4
Kaufmann, M.5
Shultz, K.6
Burns, M.7
Kumar, J.8
Yuan, J.9
Nguyen, J.10
-
2
-
-
0343270310
-
RTPG-A Dynamic Biased Pseudo-Random Test Program Generator for Processor Verification
-
July
-
A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "RTPG-A Dynamic Biased Pseudo-Random Test Program Generator for Processor Verification," IBM Technical Report 88.290, July 1990.
-
(1990)
IBM Technical Report 88.290
-
-
Aharon, A.1
Bar-David, A.2
Dorfman, B.3
Gofman, E.4
Leibowitz, M.5
Schwartzburd, V.6
-
4
-
-
0029723878
-
Functional Verification Methodology of Chameleon Processor
-
F. Casaubieilh, A. McIsaac, M. Benjamin, M. Bartley, F. Pogodalla, F. Rocheteau, M. Belhadj, J. Eggleton, G. Mas, F. Barrett, and C. Berthet, "Functional Verification Methodology of Chameleon Processor," Proc. of the Design Automation Conf., 1996, pp. 421-426.
-
(1996)
Proc. of the Design Automation Conf.
, pp. 421-426
-
-
Casaubieilh, F.1
McIsaac, A.2
Benjamin, M.3
Bartley, M.4
Pogodalla, F.5
Rocheteau, F.6
Belhadj, M.7
Eggleton, J.8
Mas, G.9
Barrett, F.10
Berthet, C.11
-
5
-
-
0031639694
-
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor
-
S. Taylor, M. Quinn, D. Brown, N. Dohm, S. Hildebrandt, J. Huggins, and C. Farney, "Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor," Proc. of the Design Automation Conf., 1998, pp. 638-643.
-
(1998)
Proc. of the Design Automation Conf.
, pp. 638-643
-
-
Taylor, S.1
Quinn, M.2
Brown, D.3
Dohm, N.4
Hildebrandt, S.5
Huggins, J.6
Farney, C.7
-
6
-
-
0031630267
-
Functional Verification of Large ASICs
-
A. Evans, A. Silburt, G. Vrckovnik, T. Brown, M. Dufresne, G. Hall, T. Ho, and Y. Liu, "Functional Verification of Large ASICs.," Proc. of the Design Automation Conf., 1998, pp. 650-655.
-
(1998)
Proc. of the Design Automation Conf.
, pp. 650-655
-
-
Evans, A.1
Silburt, A.2
Vrckovnik, G.3
Brown, T.4
Dufresne, M.5
Hall, G.6
Ho, T.7
Liu, Y.8
-
8
-
-
0002755438
-
Integrating Model Checking into the Semiconductor Design Flow
-
March
-
C. Pixley, "Integrating Model Checking Into the Semiconductor Design Flow," Computer Design's Electronic Systems Journal, pp. 67-74, March 1999.
-
(1999)
Computer Design's Electronic Systems Journal
, pp. 67-74
-
-
Pixley, C.1
-
10
-
-
0022769976
-
Graph-based Algorithms for Boolean Function Manipulation
-
Aug.
-
R. Bryant, "Graph-based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, Vol. C-35, pp. 677-691, Aug. 1986.
-
(1986)
IEEE Transactions on Computers
, vol.C-35
, pp. 677-691
-
-
Bryant, R.1
-
11
-
-
35048900689
-
20 States and Beyond
-
20 States and Beyond," Information and Computation, Vol. 98, No. 2, pp. 142-170, 1992.
-
(1992)
Information and Computation
, vol.98
, Issue.2
, pp. 142-170
-
-
Burch, J.R.1
Clarke, E.M.2
McMillan, K.L.3
Dill, D.L.4
-
13
-
-
0004000918
-
The 68060 Microprocessor Functional Design and Verification Methodology
-
J. Freeman, R. Duerden, C. Taylor, and M. Miller, "The 68060 Microprocessor Functional Design and Verification Methodology," On-Chip Systems Design Conference, 1995, pp. 10.1-10.14.
-
(1995)
On-chip Systems Design Conference
, pp. 101-1014
-
-
Freeman, J.1
Duerden, R.2
Taylor, C.3
Miller, M.4
-
14
-
-
0001314320
-
Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-random Test Program Generator
-
July
-
A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-random Test Program Generator," IBM Systems Journal, Vol. 30, No. 4, pp. 527-538, July 1991.
-
(1991)
IBM Systems Journal
, vol.30
, Issue.4
, pp. 527-538
-
-
Aharon, A.1
Bar-David, A.2
Dorfman, B.3
Gofman, E.4
Leibowitz, M.5
Schwartzburd, V.6
-
15
-
-
0001644351
-
Constraint Solving for Test Case Generation - A Technique for High Level Design Verification
-
A.K. Chandra and VS. Iyengar, "Constraint Solving for Test Case Generation - A Technique for High Level Design Verification," Proc. Intl. Conf. on Computer Design, 1992, pp. 245-248.
-
(1992)
Proc. Intl. Conf. on Computer Design
, pp. 245-248
-
-
Chandra, A.K.1
Iyengar, V.S.2
-
16
-
-
0000574517
-
AVPGEN - A Test Case Generator for Architecture Verification
-
June
-
A. Chandra, V. Iyengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal, "AVPGEN - A Test Case Generator for Architecture Verification," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 2, pp. 188-200, June 1995.
-
(1995)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.3
, Issue.2
, pp. 188-200
-
-
Chandra, A.1
Iyengar, V.2
Jameson, D.3
Jawalekar, R.4
Nair, I.5
Rosen, B.6
Mullen, M.7
Yoon, J.8
Armoni, R.9
Geist, D.10
Wolfsthal, Y.11
-
17
-
-
0027880685
-
Algebraic Decision Diagrams and their Applications
-
R.I. Bahar, E.A. Frohm, C.M. Gaona, G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Algebraic Decision Diagrams and their Applications," Proc. Intl. Conf. on Computer-Aided Design, 1993, pp. 188-192.
-
(1993)
Proc. Intl. Conf. on Computer-aided Design
, pp. 188-192
-
-
Bahar, R.I.1
Frohm, E.A.2
Gaona, C.M.3
Hachtel, G.D.4
Macii, E.5
Pardo, A.6
Somenzi, F.7
-
18
-
-
0028016578
-
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finit State Machine
-
G.D. Hachtel, E. Machii, A. Pardo, and F. Somenzi, "Symbolic Algorithms to Calculate Steady-State Probabilities of a Finit State Machine," The European Design and Test Conference, 1994, pp. 214-218.
-
(1994)
The European Design and Test Conference
, pp. 214-218
-
-
Hachtel, G.D.1
Machii, E.2
Pardo, A.3
Somenzi, F.4
-
19
-
-
0002962651
-
Equivalence of Free Boolean Graphs Can Be Decided Probabilistically in Polynomial Time
-
M. Blum, A.K. Chandra, and M.N. Wegman, "Equivalence of Free Boolean Graphs Can Be Decided Probabilistically in Polynomial Time," Information Processing Letters, Vol. 10, No. 2, pp. 80-82, 1980.
-
(1980)
Information Processing Letters
, vol.10
, Issue.2
, pp. 80-82
-
-
Blum, M.1
Chandra, A.K.2
Wegman, M.N.3
-
20
-
-
0027794338
-
A BDD-based Algorithm for Computation of Exact Fault Detection Probabilities
-
R. Krieger, B. Becker, and R. Sinkovic, "A BDD-based Algorithm for Computation of Exact Fault Detection Probabilities," International Symposium on Fault-Tolerant Computing, 1993, pp. 186-195.
-
(1993)
International Symposium on Fault-tolerant Computing
, pp. 186-195
-
-
Krieger, R.1
Becker, B.2
Sinkovic, R.3
-
21
-
-
0025558645
-
Efficient Implementation of a BDD Package
-
June
-
K. Brace, R. Rudell, and R. Bryant, "Efficient Implementation of a BDD Package," Proc. of the Design Automation Conf., June 1990, pp. 40-45.
-
(1990)
Proc. of the Design Automation Conf.
, pp. 40-45
-
-
Brace, K.1
Rudell, R.2
Bryant, R.3
-
22
-
-
0004000699
-
-
F. Somenzi, I. Bahar, H. Cho, E. Frohm, C. Gaona, C. Hua, J.Y. Jang, S.W. Jeong, B. Kumthekar, E. Macii, B. Manne, I.H. Moon, C. Musfeldt, S. Panda, A. Pardo, B. Plessier, K. Ravi, H. Shin, A. Shuler, and J. Sivesind, "CUDD: CU Decision Diagram Package," ftp://vlsi.colorado.edu/pub/
-
CUDD: CU Decision Diagram Package
-
-
Somenzi, F.1
Bahar, I.2
Cho, H.3
Frohm, E.4
Gaona, C.5
Hua, C.6
Jang, J.Y.7
Jeong, S.W.8
Kumthekar, B.9
Macii, E.10
Manne, B.11
Moon, I.H.12
Musfeldt, C.13
Panda, S.14
Pardo, A.15
Plessier, B.16
Ravi, K.17
Shin, H.18
Shuler, A.19
Sivesind, J.20
more..
|