Low-power technique for on-chip memory using biased partitioning and access concentration

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 275-278

  Kawabe, Naoyuki ^a   Usami, Kimiyoshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CODES (SYMBOLS); COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; LSI CIRCUITS;

ACCESS FREQUENCY PREDICTION; BIASED PARTITIONING AND ACCESS CONCENTRATION TECHNIQUE; CODE MOTION; MOVING PICTURE EXPERT GROUP; ON CHIP MEMORY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033711828     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)