Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16 μm CMOS test chip

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 1087-1094

  Budell, T ^a   Audet, J ^a   Kent, D ^a   Libous, J ^a   O'Connor, D ^a   Rosser, S ^a   Tremble, E ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FLIP CHIP DEVICES; SIGNAL NOISE MEASUREMENT;

BALL GRID ARRAY; FLIP CHIP MULTILAYER PACKAGES; SWITCHING NOISE MEASUREMENT;

ELECTRONICS PACKAGING;

EID: 0034838083     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Measurement, modeling and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA
2. Delta-I modeling approximations for single chip modules
3. Characterization of flip chip CMOS ASIC simultaneous switching noise on multilayer organic and ceramic BGA/CGA packages
4. Modeling, measurement and simulation of simultaneous switching noise
5. Electrical design and evaluation of organic and ceramic flip-chip package technologies for deep sub-micron CMOS ASICS
6. A high performance, low stress, laminate ball grid array flip chip carrier
7. HyperBGA: A high performance, low stress, laminate ball grid array flip chip carrier