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Volumn , Issue , 2001, Pages 378-383

Design and thermo-mechanical analysis of a dimple-array interconnect technique for power semiconductor devices

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; COMPUTER AIDED DESIGN; PERFORMANCE; RELIABILITY; SEMICONDUCTOR DEVICES; SHEET METAL; SOLDERED JOINTS; SOLDERING ALLOYS; THERMOANALYSIS;

EID: 0034838074     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (20)
  • 2
    • 0003752749 scopus 로고    scopus 로고
    • Modeling, analysis, and design of distributed power electronics system based on building block concept
    • Ph.D. Dissertation, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA, May
    • (1999)
    • Xing, K.1
  • 4
  • 5
    • 0002395754 scopus 로고    scopus 로고
    • New power switch packaging technologies
    • May
    • (2000) PCIM , pp. 28-30
    • Ericsen, T.1
  • 6
    • 0001822366 scopus 로고    scopus 로고
    • ThinPak technology shrinks power modules, power hybrids and ultra-high speed switching devices
    • May
    • (2000) PCIM , pp. 32-38
    • Temple, V.1
  • 9
    • 0001983341 scopus 로고    scopus 로고
    • Bottomless SO-8 package boosts MOSFET performance
    • May
    • (2000) PCIM , pp. 110
    • Klein, J.1
  • 11
    • 0003535583 scopus 로고    scopus 로고
    • A dimple-array interconnect technique for semiconductor devices
    • Virginia Tech Intellectual Properties, Inc. patent disclosure, VTIP Disclosure No.: 00-012
    • Lu, G.-Q.1    Wen, S.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.