An ESD protection circuit for mixed-signal ICs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 493-496

  Feng, Haigang ^a   Gong, Ke ^a   Wang, Albert Z ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); OPTIMIZATION;

ELECTROSTATIC DISCHARGE; MIXED SIGNAL INTEGRATED CIRCUITS; PROTECTION CIRCUIT; RADIO FREQUENCY INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034829045     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2001.929828     Document Type: Article

References (5)

1. A comparison study of ESD protection for RFICs
2. A new design for complete on-chip ESD protection
3. Capacitor-couple ESD protection circuit for deep-submicron LV CMOS ASIC
4. A novel design methodology using simulation for on-chip ESD protection for ICs