New design methodology using simulation for on-chip ESD protection designs for integrated circuits

International Conference on Solid-State and Integrated Circuit Technology Proceedings

Volumn , Issue , 1998, Pages 509-512

  Wang, Albert Z ^a   Tsay, Chen H ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; OVERCURRENT PROTECTION; OVERVOLTAGE PROTECTION; SEMICONDUCTOR DEVICE MODELS;

ELECTROSTATIC DISCHARGE (ESD);

INTEGRATED CIRCUIT LAYOUT;

EID: 0032226860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (5)