A platform-based highly parallel digital signal processor

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 305-308

  Richter, T ^a   Drescher, W ^b   Engel, F ^a   Kobayashi, S ^c   Nikolajevic, V ^a   Weiss, M ^b   Fettweis, G ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b Systemonic AG   (Germany)

^c Asahi Chemical   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MOBILE TELECOMMUNICATION SYSTEMS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; PARALLEL PROCESSING SYSTEMS;

CONCEPT ON APPLICATION TAILORED SIGNAL PROCESSOR; HIGHLY PARALLEL DIGITAL SIGNAL PROCESSOR; INPUT OUTPUT PROCESSORS;

DIGITAL SIGNAL PROCESSING;

EID: 0034828972     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2001.929787     Document Type: Article

References (7)

1. DSP cores for mobile communications: Where are we going
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3. An architectural study of a digital signal processor for block codes
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5. Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors
6. A new scalable DSP architecture for system on chip (SOC) domains