Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2001, Pages 167-172

  Hanyu, Takahiro ^a   Kameyama, Michitaka ^a   Shimabukuro, Katsuhiko ^b   Zukeran, Chotei ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b UNIVERSITY OF THE RYUKYUS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LOGIC CIRCUITS; MASKS; MOS DEVICES; THRESHOLD VOLTAGE;

MASK-PROGRAMMABLE LOGIC ARRAYS (PLA);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034828944     PISSN: 0195623X     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISMVL.2001.924568     Document Type: Article

References (12)

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8. A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications
9. A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming