Design and evaluation of a 4-valued universal-literal CAM for cellular logic image processing

IEICE Transactions on Electronics

Volumn E80-C, Issue 7, 1997, Pages 948-954

  Hanyu, Takahiro ^a   Arakaki, Manabu ^a   Kameyama, Michitaka ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Floating gate mos transistor; Fully parallel template matching; Logic value conversion (LVC); Single transistor cell; Threshold operation

Indexed keywords

IMAGE PROCESSING; MOS DEVICES; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; TRANSISTORS;

CELLULAR LOGIC IMAGE PROCESSING; LOGIC VALUE CONVERSION (LVC); PARALLEL TEMPLATE MATCHING;

ASSOCIATIVE STORAGE;

EID: 0031192502     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

1. J.G. Delgado-Frias and W.R. Moore, "VLSI for Artificial Intelligence," Kluwer Academic Publishers, USA, 1989.
2. K.E. Grosspietsch, "Associative processors and memories: A survey," IEEE Micro, vol.12, no.3, pp.12-19, June 1992.
3. P.P. Herrmann and C.G. Sodini, "A dynamic associative processor for machine vision applications," IEEE Micro, vol.12, no.3, pp.31-41, June 1992.
4. R. Storer, M.R. Pout, A.R. Thomson, E.L. Dagless, A.W.G. Duller, A.P. Marriott, and P.J. Hicks, "An associative processing module for a heterogeneous, vision architecture," IEEE Micro, vol.12, no.3, pp.42-55, June 1992.
5. T. Higuchi and M. Kameyama, "Multiple-Valued Digital Processing System," Shokodo Co. Ltd., Tokyo, 1989.
6. K.C. Smith and P.O. Gulak, "Prospects for multiple-valued integrated circuits," IEICE Trans. Electron., vol.E76-C, no.3, pp.372-382, March 1993.
7. T. Hanyu, M. Kameyama, and T. Higuchi, "Prospects of multiple-valued VLSI processors," IEICE Trans. Electron., vol.E76-C, no.3, pp.383-392, March 1993.
8. T. Hanyu, M. Arakaki, and M. Kameyama, "Quaternary universal-literal CAM for cellular logic image processing," Proc. of 1996 Int. Symp. on MVL, pp.224-229, May 1996.
9. T. Hanyu, M. Arakaki, and M. Kameyama, "2-transistorcell 4-valued universal-literal CAM for a cellular logic image processor," IEEE Int. Solid-State Circuits Conf. TP2.5, pp.46-47, Feb. 1997.
10. K.C. Smith, "The prospects for multiple-valued logic: A technology and applications view," IEEE Trans. Comput., vol.C-30, pp.619-634, Sept. 1981.
11. T. Blyth, S. Khan, and R. Simko, "A non-volatile analog storage device using EEPROM technology," Dig. IEEE Int. Solid~-State Circuits Conf., TP11.7, pp.192-193, Feb. 1991.
12. M. Kameyama, K. Suzuki, and T. Higuchi, "Image processing algorithms for a multiple-valued array processor," Proc. of the 1983 Int. Symp. on Multiple-Valued Logic, pp.236-241, May 1983.
13. T. Yamagata, M. Mihara, T. Hamamoto, Y. Murai, T. Kobayashi, M. Yamada, and H. Ozaki, "288kb fully parallel content addressable memory using a stacked-capacitor cell structure," IEEE J. Solid-State Circuits., vol.27, no.12, pp. 1927-1933, Dec. 1992.