Substrate current protection in smart power IC's

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2000, Pages 169-172

  Gonnard, O ^a   Charitat, G ^a   Lance, P ^a   Stefanov, E ^a   Suquet, M ^a   Bafleur, M ^a   Mauran, N ^a   Peyre Lavigne, A ^a  

^a ON SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; ELECTRIC CURRENTS; GATES (TRANSISTOR); SEMICONDUCTOR DIODES; SUBSTRATES;

PARASITIC CURRENT; SMART POWER INTEGRATED CIRCUIT;

POWER INTEGRATED CIRCUITS;

EID: 0034447762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. The influence of an IGBT on CMOS latch up in power IC's
2. Interaction between monolithic junction isolated lateral insulated gate bipolar transistors
3. Smart power approaches VLSI complexity
4. A novel crosstalk isolation structure for bulk CMOS power IC's
5. DC substrate coupling between LDMOS and CMOS devices in hyperintegration I technology