High resistance via induced by marginal barrier metal step coverage and F diffusion

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2001, Pages 183-186

  Dai, J Y ^a   Loh, S K ^a   Tee, S F ^a   Tay, C L ^a   Ansari, S ^a   Er, E ^a   Redkar, S ^a  

^a CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION; ELECTRIC RESISTANCE; ENERGY DISPERSIVE SPECTROSCOPY; FAILURE ANALYSIS; FLUORINE; INTEGRATED CIRCUIT TESTING; METALLIZING; SCANNING ELECTRON MICROSCOPY; SPUTTER DEPOSITION; STATIC RANDOM ACCESS STORAGE; TIN COMPOUNDS; TRANSMISSION ELECTRON MICROSCOPY;

BARRIER METAL STEP COVERAGE; SCANNING TRANSMISSION ELECTRON MICROSCOPY; SUBMICRON MULTILEVEL METALLIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0034818267     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)