Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in RAM

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2000, Pages 77-79

  Perungulam, Srikanth ^a   Wills, Scott ^a   Mekras, Greg ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ELECTRIC CONTACTS; ELECTRIC RESISTANCE; ENERGY DISPERSIVE SPECTROSCOPY; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; FOCUSING; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; ION BEAMS; PROCESS CONTROL; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; TITANIUM NITRIDE; TRANSMISSION ELECTRON MICROSCOPY; VOLTAGE MEASUREMENT;

FOCUSED ION BEAM (FIB); MAGNIFICATION MEASUREMENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 1542300874     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. nd Edition, 564 (1992).
2. rd Edition (1997).
3. th Edition, 315 (1999).
4. Lancy Tsung, Adolfo Anciso, presented at ISTFA '98.