Architectural power optimization by bus splitting

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 612-616

  Hsieh, Cheng Ta ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POWER OPTIMIZATION; POWER SAVINGS;

DATA TRANSFER; ELECTRONIC DATA INTERCHANGE; EXHIBITIONS;

BUSES;

EID: 30844434702     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840848     Document Type: Conference Paper

References (5)

1. Y. Nakagome et al. "Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's," in IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, pp. 414-419, 1993.
2. E. Macii, M. Pedram and F. Somenzi, "High level power modeling, estimation and optimization," IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, pp. 1061-1079, Nov. 1998.
3. M. R. Garey, D. S. Johnson, "Computer and Intractability, A Guide to the Theory of NP-Completeness," W.H. Freeman and Company, 1979.
4. A. Leon-Garcia, " Probability and Random Processes for Electrical Engineering," Second Edition, Addison Wesley, 1993.
5. T. Lengauer, "Combinatorial Algorithms for Integrated Circuit Layout," John Wiley & Sons, 1990.