Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Proceedings of the International Conference on Supercomputing

Volumn Part F129670, Issue , 1993, Pages 67-76

  Yeh, Tse Yu ^a   Marr, Deborah T ^a   Patt, Yale N ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; HARDWARE;

ADDRESS CACHES; BASIC BLOCKS; BRANCH PREDICTION; FLOATING POINTS; HARDWARE MECHANISM; HIGH PERFORMANCE COMPUTERS; INSTRUCTION FETCH; SUPERSCALAR;

COMPUTER HARDWARE;

EID: 84969344997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/165939.165956     Document Type: Conference Paper

References (11)

1. J.E. Smith, "A Study of Branch Prediction Strategies", Proceedings of the 8th International Symposium on Computer Architecture, (May 1981), pp. 135-148.
2. J. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, (Jan. 1984), pp. 6-22.
3. R. Colwell, R. Nix, J. O'Donnell, D. Papworth, and P. Rodman, "A VLIW Architecture for a Trace Scheduling Compiler," Proc of the 2nd Intl Conf on Architectural Support for Programming Languages and Operating Systems, (Oct. 1987), pp. 180-192.
4. B.R. Rau, D. Yen, W. Yen, and R. Towle, "The Cydra 5 Departmental Supercomputer - Design Philosophies, Decisions, and Trade-offs," IEEE Computer, (Jan. 1989), pp. 12-35.
5. M. Butler, T-Y Yeh, Y.N. Patt, M. Alsup, H. Scales, and M. Shebanow, "Instruction Level Parallelism is Greater Than Two", Proceedings of the 18th International Symposium on Computer Architecture, (May 1991), pp. 276-286.
6. T-Y Yeh and Y.N. Patt, "Two-Level Adaptive Branch Prediction", The 24th ACM/IEEE Intl Sym and Wkshop on Microarchitecture, (Nov. 1991), pp. 51-61.
7. T-Y Yeh and Y.N. Patt "Alternative Implementations of Two-Level Adaptive Branch Prediction," Proceedings of the 19th International Symposium on Computer Architecture, (May 1992), pp. 124-134.
8. S-T Pan, K. So, and J.T. Rahmeh, "Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation," Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, (Oct. 1992), pp. 76-84.
9. T-Y Yeh and Y.N. Patt "A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution," Proc of the 25th International Symposium on Microarchitecture, (Dec. 1992), pp. 129-139.
10. T-Y Yeh and Y.N. Patt "A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History," Proceedings of the 20th International Symposium on Computer Architecture, (May 1993).
11. W. Hwu, S. Mahlke, W. Chen, P. Chang, N. Warter, R. Bringmann, R. Ouellete, R. Hank, T. Kiyohara, G. Haab, J. Holm, and D. Lavery, "The superblock: An effective technique for VLIW and superscalar compilation," The Journal of Supercomputing, January 1993.