Decoupled value prediction on trace processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 231-240

  Lee, Sang Jeong ^a   Wang, Yuan ^a   Yew, Pen Chung ^a  

^a Soonchunhyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DATA HANDLING; DYNAMIC PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SUPERVISORY AND EXECUTIVE PROGRAMS;

DATA DEPENDENT INSTRUCTIONS; DECOUPLED VALUE PREDICTION; TRACE PROCESSORS;

DATA FLOW ANALYSIS;

EID: 0034581168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

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4. Alternative fetch and issue policies for the trace cache fetch mechanism
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6. Speculative execution based on value prediction
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10. Exploiting basic block value locality with basic block reuse
11. Path - Based next trace prediction
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13. Combining branch predictors
14. A scalable front-end architecture for fast instruction delivery
15. Trace cache: A low latency approach to high bandwidth instruction fetching
16. Trace processors
17. Efficient and accurate value prediction using dynamic classification
18. Efficacy and performance impact of value prediction
19. The predictability of data values
20. Highly accurate data value predictions using hybrid predictor
21. Two-level adaptive branch prediction