Testing domino circuits in SOI technology

Proceedings of the Asian Test Symposium

Volumn , Issue , 2000, Pages 441-446

  MacDonald, Eric ^a   Touba, Nur A ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOMINO CIRCUITS; LEAKAGE SENSITIVITY;

INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SILICON ON INSULATOR TECHNOLOGY;

LOGIC CIRCUITS;

EID: 0034513668     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. C.T. Chuang, P.-F. Lu, C.J. Anderson, "SOI for Digital CMOS VLSI: Design Considerations and Advances", Proceedings of the IEEE, pp. 689-720, April, 1998.
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5. K. Nowka, T. Galambos, "Circuit Design Techniques for a Gigahertz Integer Microprocessor", Proc. of International Conference on Computer Design, pp. 11-16, 1998.
6. M. Pelella, J. Fossum, D. Suh, S. Krishnan, K. Jenkins, "Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in PD/SOI MOSFETs", Proc. of IEEE International SOI Conference, pp. 8-9, 1995.
7. G. Shahidi, A. Ajmera, F. Assaderaghi, R. Bolam, H. Hovel, E. Leobandung, W. Raush, D. Sandana. D. Schepis, L. Wagner, L. Wissel, K. Wu, B. Davari, "Device and Circuit Issues in SO1 Technology", Proc. of IEEE Custom Integrated Circuits Conference, pp. 339-346, 1998.
8. P. Srivastava, A. Pua, L. Welch, "Issues in the Design of Domino Logic Circuits", Proc. of 8th Great Lakes Symposium on VLSI, pp.108-115, 1998.
9. A. Wei, D. Antoniadis, "Measurement of Transient Effects in SOI DRAMERAM Access Transistors", IEEE Electron Device Letters, vol. 17, no. 5, pp. 193-195, May, 1996.