LDMOS implementation by large tilt implant in 0.6 μm BCD5 process, flash memory compatible

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1996, Pages 75-78

  Contiero, C ^a   Galbiati, P ^a   Palmieri, M ^a   Vecchi, L ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MOS DEVICES; NONVOLATILE STORAGE; PROM; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR STORAGE; VLSI CIRCUITS;

FLASH NONVOLATILE MEMORIES; TILT IMPLANTATION TECHNIQUE;

POWER ELECTRONICS;

EID: 0029712880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)