The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2000, Pages 263-266

  Trajkovic, T ^a   Udrea, F ^a   Waind, P R ^a   Amaratunga, G A J ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC FIELDS; ELECTRIC POWER SUPPLIES TO APPARATUS; INSULATED GATE BIPOLAR TRANSISTORS; INTERFACES (MATERIALS); MOISTURE; PASSIVATION; SEMICONDUCTOR DOPING;

BREAKDOWN TERMINATION TECHNIQUE; DYNAMIC PARASITIC CHARGE; FLOATING-RING EDGE TERMINATION; STATIC PARASITIC CHARGE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0034447178     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Blocking capability of planar devices with field limiting rings
2. Surface breakdown in silicon planar diodes equipped with field plate
3. Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions
4. Comparison of DMOS/IGBT-compatible high voltage termination structures and passivation techniques
5. The effect of charge in junction termination extension passivation dielectrics
6. High-voltage planar devices using field-plate and semiresistive layers
7. Diffused spiral junction termination structure: Modeling and realization
8. Efficiency of junction termination techniques vs oxide trapped charges
9. 1.4kV, 25A, PT and NPT trench IGBTs with optimum forward characteristics