Imprint lithography using triple-layer-resist and its application to metal-oxide-silicon field-effect-transisor fabrication

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 39, Issue 12 B, 2000, Pages 7080-7085

  Nakamura, Hiroyuki ^a   Baba, Akiyoshi ^a   Asano, Tanemasa ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Gate oxide integrity; Imprint lithography; MOSFET; Pattern transfer; Photolithography; Porous silicon; Triple layer resist

Indexed keywords

MOSFET DEVICES; POLYMETHYL METHACRYLATES; POROUS SILICON; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

IMPRINT LITHOGRAPHY; TRIPLE-LAYER RESISTS;

PHOTORESISTS;

EID: 0034429038     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.39.7080     Document Type: Article

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