Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 402-403,-473

  Shibayama, A ^a   Mizuno, M ^a   Abiko, H ^a   Ono, A ^a   Masuoka, S ^a   Matsumoto, A ^a   Tamura, T ^a   Yamada, Y ^a   Nishizawa, A ^a   Kawamoto, H ^a   Inoue, K ^a   Nakazawa, Y ^a   Sakai, I ^a   Yamashina, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS; SIGNAL GENERATORS;

LOCAL CLOCK GENERATOR (LCG); PHASE DETECTORS; RACE FREE IMPULSE LATCH CIRCUITS;

TIMING CIRCUITS;

EID: 0031703198     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)