New-generation parallel computer and its performance evaluation

Future Generation Computer Systems

Volumn 17, Issue 3, 2000, Pages 315-333

  Ziavras, Sotirios G ^a   Grebel, Haim ^a   Chronopoulos, Anthony T ^b   Marcelli, Florent ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

^b One UTSA Circle   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; FIBER OPTIC NETWORKS; OPTICAL COMMUNICATION; RESPONSE TIME (COMPUTER SYSTEMS); TIME DIVISION MULTIPLEXING; WAVELENGTH DIVISION MULTIPLEXING;

GENERALIZED HYPERCUBES;

PARALLEL PROCESSING SYSTEMS;

EID: 0034315612     PISSN: 0167739X     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-739X(00)00082-0     Document Type: Article

References (32)

1. K. Aly, P. Dowd, Parallel computer reconfigurablility through optical interconnects, in: International Conference on Parallel Processing, 1992, pp. I:105-137.
2. Bhuyan L.N., Agrawal D.P. Generalized hypercube and hyperbus structures for a computer network. IEEE Trans. Comput. 33(4):1984;323-333.
3. L. Camp, et al., Guided-wave and free space optical interconnect for parallel processing systems: a comparison, Appl. Opt. 33 (1994) 6168-6180.
4. A.L. Cox, et al., Software versus hardware shared-memory implementation: a case study, in: International Symposium on Computing Architecture, 1994, pp. 106-117.
5. Dally W.J., Seitz C.L. The torus routing chip. Distrib. Comput. 1:1986;187-196.
6. W.J. Dally, Network and processor architecture for message-driven computers, in: R. Suaya, G. Birtwistle (Eds.), VLSI and Parallel Computation, Morgan Kaufmann, Los Altos, CA, 1990, pp. 140-222.
7. Fragopoulou P., Akl S.G., Meijer H. Optimal communication primitives on the generalized hypercube network. J. Parallel Distrib. Comput. 32:1996;173-187.
8. E. Frietman, et al., Parallel optical interconnects: implementation of optoelectronics in multiprocessors architecture, Appl. Opt. 29 (1990).
9. Findings and Recommendations, PetaFLOPS Software Summer Study (PetaSoft'96), June 1996.
10. M. Kajita, K. Kasahara, T.J. Kim, I. Ogura, I. Redmond, E. Schenfeld, Free-space wavelength division multiplexing optical interconnections for massively parallel processing systems, in: Int'l. Top. Meet. Opt. Comput. 1996, pp. 24-25.
11. D. Lenoski, et al., The stanford FLASH multiprocessor, IEEE Comput. 3 (1992) 63-79.
12. Li X., Ziavras S.G., Manikopoulos C.N. Parallel DSP algorithms on turboNet: an experimental hybrid message-passing/shared-memory architecture. Conc.: Pract. Exp. 8(5):1996;387-411.
13. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association (SIA), 1994.
14. D.A. Patterson, Teraflops design in eight easy steps, Sci. Am. (January 1991) 104-105.
15. Pease III M.C. The indirect binary. n -cube microprocessor array IEEE Trans. Comput. C-26(5):1977;458-473.
16. Qiao C., Melhem R. Reducing communication latency with path multiplexing in optically interconnected multiprocessor systems. IEEE Trans. Parallel Distrib. Syst. 8(2):1997;97-108.
17. Seitz C.L. Concurrent VLSI architectures. IEEE Trans. Comput. C-33(12):1984;1247-1265.
18. J. Senior, Optical Fiber Communication, 2nd Edition, Prentice-Hall, Englewood Cliffs, NJ, 1992.
19. Seshita T., Ikeda Y., Wakimoto H., Ishida K., Terada T., Matsunaga T., Suzuki T., Kitaura Y., Uchitomi N. A 20 GHz 8 bit multiplexer IC implemented with. 0.5μm WNx/W-Gate GaAs MESFET's IEEE J. Solid-State Circ. 29(12):1994;1583-1587.
20. Soda M., Tezuka H., Sato F., Hashimoto T., Nakamura S., Tatsumi T., Suzaki T., Tashiro T. Si-Analog IC's for 20 Gb/s optical receiver. IEEE J. Solid-State Circ. 29(12):1994;1577-1581.
21. Szymanski T. Hypermeshes: optical interconnection networks for parallel computing. J. Parallel Distrib. Comput. 26:1995;1-23.
22. Tsay S.C., Grebel H. Design of transverse holographic optical interconnect. Appl. Opt. 33:1994;6747-6752.
23. A. Yariv, Optical Electronics, 4th Edition, Saunders, Belmont, CA, 1991.
24. L.D. Wittie, Communication structures for large networks of multicomputers, IEEE Trans. Comput. C-30 (4) (1981).
25. Ziavras S.G. On the problem of expanding hypercube-based systems. J. Parallel Distrib. Comput. 16(1):1992;41-53.
26. Ziavras S.G. RH: a versatile family of reduced hypercube interconnection networks. IEEE Trans. Parallel Distrib. Syst. 5(11):1994;1210-1220.
27. S.G. Ziavras, Generalized reduced hypercube interconnection networks for massively parallel computers, in: D.F. Hsu, A. Rosenberg, D. Sotteau (Eds.), Networks for Parallel Computations, American Mathematical Society, Providence, RI, 1995, pp. 307-325.
28. Ziavras S.G. Scalable multifolded hypercubes for versatile parallel computers. Parallel Process. Lett. 5(2):1995;241-250.
29. Ziavras S.G., Mukherjee A. Data broadcasting and reduction, prefix computation, and sorting on reduced hypercube parallel computers. Parallel Comput. 22:1996;595-606.
30. S.G. Ziavras, H. Grebel, A.T. Chronopoulos, A low-complexity parallel system for gracious, scalable performance. Case study for near PetaFLOPS computing, in: Proceedings of the Sixth Symposium on Front. Mass. Parallel Computations, Special Session New Millennium Computing Point Designs, 1996, pp. 363-370.
31. S.G. Ziavras, H. Grebel, A.T. Chronopoulos, A scalable/feasible parallel computer implementing electronic and optical interconnections for 156 TeraOPS minimum performance, in: PetaFLOPS Arch. Workshop, 1996, pp. 179-209.
32. Ziavras S.G. Investigation of various mesh architectures with broadcast buses for high-performance computing. VLSI Des. 9(1):1999;29-54.