Design of a lower-error fixed-width multiplier for speech processing application

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1999, Pages

  Van, Lan Da ^a   Wang, Shuenn Shyang ^a   Tenqchen, Shing ^a   Feng, Wu Shiung ^a   Jeng, Bor Shenn ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR COMPENSATION; FIR FILTERS; INTEGRATED CIRCUIT LAYOUT; LOW PASS FILTERS; MATHEMATICAL MODELS; SPEECH PROCESSING; VLSI CIRCUITS;

BAUGH-WOOLEY ALGORITHM; FIXED WIDTH MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 17644433972     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (3)