Functionally testable path delay faults on a microprocessor

IEEE Design and Test of Computers

Volumn 17, Issue 4, 2000, Pages 6-14

  Lai, Wei Cheng ^a,b   Krstic, Angela ^a   Cheng, Kwang Ting ^a,b,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; CONSTRAINT THEORY; CORRELATION THEORY; DATA REDUCTION; FLIP FLOP CIRCUITS; OPTIMIZATION; PATTERN MATCHING; SEMICONDUCTOR DEVICES;

PATH DELAY FAULTS; TEST PROGRAMS;

MICROPROCESSOR CHIPS;

EID: 0034291336     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.895002     Document Type: Article

References (9)

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