Testable path delay fault cover for sequential circuits

European Design Automation Conference - Proceedings

Volumn , Issue , 1996, Pages 220-226

  Krstic, Angela ^a   Chakradhar, Srimat T ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; DELAY CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; VECTORS;

BENCHMARK CIRCUITS; COMBINATIONAL PATH; DELAY DEFECTS; FAULT MODEL; MULTI LEVEL NETLISTS; TESTABLE PATH DELAY FAULT COVER;

ALGORITHMS;

EID: 0029747881     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)