Sequential test generation based on circuit pseudo-transformation

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 62-67

  Ohtake, Satoshi ^a   Inoue, Tomoo ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PSEUDO TRANSFORMATION (CPT); SEQUENTIAL TEST GENERATION;

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT TESTING;

SEQUENTIAL CIRCUITS;

EID: 0031373434     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. Abramovici, M. A. Breuer and A. D. Friedman: Digital System Testing and Testable Design, IEEE Press, 1995.
2. A. Balakrishnan and S. T. Chakradhar: Software Transformations for Sequential Test Generation, IEEE 4th Asian Test Symposium, pp. 266-272, November 1995.
3. G. D. Micheli: Synthesis and Optimization of Digital Circuits, McGraw-Hill, Inc., 1994.
4. R. Gupta, R. Gupta and M. A. Breuer: The BALLAST Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, Vol. 39, No. 4, pp. 538-544, April 1990.
5. H. Fujiwara, S. Ohtake and T. Takasaki: Sequential Circuit Structure with Combinational Test Generation Complexity and Its Application (in Japanese), IEICE, Vol. J80-D-I, No. 2, pp. 155-163, February 1997.
6. S. Ohtake, T. Inoue and H. Fujiwara: Sequential Test Generation Based on Circuit Pseudo-Transformation, Technical Report NAIST-ISTR97014, Nara Institute of Science and Technology, July 1997.
7. T. P. Kelsey, K. K. Saluja and S. Y. Lee: An Efficient Algorithm for Sequential Circuit Test Generation, IEEE Transactions on Computers, vol. 42, No. 11, pp. 1361-1371, November 1993.
8. S. T. Chakradhar, A. Balakrishnan and V. D. Agrawal: An Exact Algorithm for Selecting Partial Scan Flip-Flops, Proceedings of 31th ACM/IEEE Design Automation Conference, pp. 81-86, June 1994.