Single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors

Nanotechnology

Volumn 11, Issue 3, 2000, Pages 154-160

  Yamanaka, T ^a,b   Morie, T ^a   Nagata, M ^a   Iwata, A ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

^b Texas Instruments Japan Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; PROBABILITY DISTRIBUTIONS; SEMICONDUCTING SILICON;

BACKGROUND-CHARGE EFFECTS; NANOCRYSTAL FLOATING-GATE TRANSISTORS; SINGLE-ELECTRON STOCHASTIC ASSOCIATIVE PROCESSING CIRCUITS;

NANOTECHNOLOGY;

EID: 0034273494     PISSN: 09574484     EISSN: None     Source Type: Journal    
DOI: 10.1088/0957-4484/11/3/303     Document Type: Article

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