40nm gate length ultra-thin SOI n-MOSFETs with a backside conducting layer

Annual Device Research Conference Digest

Volumn , Issue , 1998, Pages 76-77

  Suzuki, Eiichi ^a   Ishii, Kenichi ^a   Kanemaru, Seigo ^a   Maeda, Tatsuro ^a   Nagai, Kiyoko ^a   Sekigawa, Toshihiro ^a  

^a ELECTROTECHNICAL LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC FORCE MICROSCOPY; ELECTRIC RESISTANCE; ELECTRON BEAM LITHOGRAPHY; GATES (TRANSISTOR); PLASMA ETCHING; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

BACKSIDE CONDUCTING LAYER; DRAIN; S FACTOR; SOURCE;

MOSFET DEVICES;

EID: 0032315814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)