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1
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0029407022
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An experimental 220 MHz 1-Gb DRAM with a distributed-column-control architecture
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Nov.
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T. Sakata, M. Horiguchi, T. Sekiguchi, S. Ueda, H. Tanaka, E. Yamasaki, Y. Nakagome, M. Aoki, T. Kaga, M. Ohkura, R. Nagai, F. Murai, T. Tanaka, S. Iijima, N. Yokoyama, Y. Gotoh, K. Shoji, T. Kisu, H. Yamashita, T. Nishida, and E. Takeda, "An experimental 220 MHz 1-Gb DRAM with a distributed-column-control architecture," IEEE J. Solid-State Circuits, vol. 30, pp. 1165-1172, Nov. 1995.
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Sakata, T.1
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Tanaka, H.5
Yamasaki, E.6
Nakagome, Y.7
Aoki, M.8
Kaga, T.9
Ohkura, M.10
Nagai, R.11
Murai, F.12
Tanaka, T.13
Iijima, S.14
Yokoyama, N.15
Gotoh, Y.16
Shoji, K.17
Kisu, T.18
Yamashita, H.19
Nishida, T.20
Takeda, E.21
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2
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0030082103
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A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture
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Feb.
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Y. Nitta, N. Sakashita, K. Shimomura, F. Okuda, H. Shimano, S. Yamakawa, A. Furukawa, K. Kise, H. Watanabe, Y. Toyoda, T. Fukada, M. Hasegawa, M. Tsukude, K. Arimoto, S. Baba, Y. Tomita, S. Komori, K. Kyuma, and H. Abe, "A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 376-377.
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ISSCC Dig. Tech. Papers
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Nitta, Y.1
Sakashita, N.2
Shimomura, K.3
Okuda, F.4
Shimano, H.5
Yamakawa, S.6
Furukawa, A.7
Kise, K.8
Watanabe, H.9
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Tsukude, M.13
Arimoto, K.14
Baba, S.15
Tomita, Y.16
Komori, S.17
Kyuma, K.18
Abe, H.19
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3
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0032204697
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A 1-Gb SDRAM with ground-level precharged bitline and nonboosted 2.1-V word line
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Nov.
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S. Eto, M. Matsumiya, M. Takita, Y. Ishii, T. Nakamura, K. Kawabata, H. Kano, A. Kitamoto, T. Ikeda, T. Koga, M. Higashiho, Y. Serizawa, K. Itabashi, O. Tsuboi, Y. Yokoyama, and M. Taguchi, "A 1-Gb SDRAM with ground-level precharged bitline and nonboosted 2.1-V word line," IEEE J. Solid-State Circuits, vol. 33, pp. 1697-1702, Nov. 1998.
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IEEE J. Solid-state Circuits
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Eto, S.1
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Kitamoto, A.8
Ikeda, T.9
Koga, T.10
Higashiho, M.11
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Itabashi, K.13
Tsuboi, O.14
Yokoyama, Y.15
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4
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0031269883
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A four-level storage 4-Gb DRAM
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Nov.
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T. Okuda and T. Murotani, "A four-level storage 4-Gb DRAM," IEEE J. Solid-State Circuits, vol. 32, pp. 1743-1747, Nov. 1997.
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IEEE J. Solid-state Circuits
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Okuda, T.1
Murotani, T.2
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5
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0028538213
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An experimental 256-Mb DRAM with boosted sense-ground scheme
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Nov.
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M. Asakura, T. Ooishi, M. Tsukude, S. Tomishima, T. Eimori, H. Hidaka, Y. Ohno, K. Arimoto, K. Fujishima, T. Nishimura, and T. Yoshihara, "An experimental 256-Mb DRAM with boosted sense-ground scheme," IEEE J. Solid-State Circuits, vol. 29, pp. 1303-1309, Nov. 1994.
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Asakura, M.1
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Hidaka, H.6
Ohno, Y.7
Arimoto, K.8
Fujishima, K.9
Nishimura, T.10
Yoshihara, T.11
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6
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0028585577
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Automatic voltage-swing reduction (AVR) scheme for ultra low power DRAMs
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June
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M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, and K. Fujishima, "Automatic voltage-swing reduction (AVR) scheme for ultra low power DRAMs," in Symp. VLSI Circuits Dig. Tech. Papers, June 1994, pp. 87-88.
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Tsukude, M.1
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Yamagata, T.5
Arimoto, K.6
Fujishima, K.7
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7
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0032662212
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High-speed DRAM architecture development
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May
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H. Ikeda and H. Inukai, "High-speed DRAM architecture development," IEEE J. Solid-State Circuits, vol. 34, pp. 685-692, May 1999.
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IEEE J. Solid-state Circuits
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Ikeda, H.1
Inukai, H.2
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8
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0033281316
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A precharged-capacitor-assissted sensing (PCAS) scheme with novel level controller low power DRAMs
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June
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T. Kono, T. Hamamoto, K. Mitsui, and Y. Konishi, "A precharged-capacitor-assissted sensing (PCAS) scheme with novel level controller low power DRAMs," in Symp. VLSI Circuits Dig. Tech. Papers, June 1999, pp. 123-124.
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Kono, T.1
Hamamoto, T.2
Mitsui, K.3
Konishi, Y.4
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9
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0742320066
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A 29-ns 64-Mb DRAM with hierarchical array architecture
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Sept.
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M. Nakamura, T. Takahashi, T. Akiba, G. Kitsukawa, M. Morino, T. Sekiguchi, I. Asano, K. Komatsuzaki, Y. Tadaki, S. Cho, K. Kajigaya, T. Tachibana, and K. Sato, "A 29-ns 64-Mb DRAM with hierarchical array architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 1302-1307, Sept. 1996.
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Nakamura, M.1
Takahashi, T.2
Akiba, T.3
Kitsukawa, G.4
Morino, M.5
Sekiguchi, T.6
Asano, I.7
Komatsuzaki, K.8
Tadaki, Y.9
Cho, S.10
Kajigaya, K.11
Tachibana, T.12
Sato, K.13
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