High-speed DRAM architecture development

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 5, 1999, Pages 685-692

  Ikeda, Hiroaki ^a   Inukai, Hidemori ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER ARCHITECTURE; INTERFACES (COMPUTER); LOGIC CIRCUITS;

SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032662212     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760380     Document Type: Article

References (5)

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2. T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, K. Yukio, Y. Fukuzo, and T. Okuda, "A 2.5 ns clock access 250 MHz SDRAM with a synchronous mirror delay," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 374-375.
3. Y. Sato, T. Suzuki, T. Aikawa, S. Fujioka, W. Fujieda, H. Kobayashi, H. Ikeda, T. Nagasawa, A. Funyu, Y. Fujii, K. Kawasaki, M. Yamazaki, and M. Taguchi, "Fast cycle RAM (FCRAM); A 20 ns random access, pipe-lined operating DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 22-25.
4. H. Ikeda, "Virtual channel memory," Nikkei Microdevices, pp. 142-149, Feb. 1998.
5. Y. Yabe, Y. Aimoto, M. Motomura, T. Takizawa, T. Miyamoto, T. Iwasaki, Y. Nakazawa, T. Fujii, M. Hamada, N. Nagai, and M. Yamashina, "Compression/decompression DRAM for unified memory systems: A 16 Mb, 200 MHz, 90-50% graphics-bandwidth reduction prototype," in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 342-343.