Dual-Loop DPLL Gear-Shifting algorithm for fast synchronization

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 7, 1997, Pages 577-586

  Kim, Beomsup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Bandwidth adjusting; Carrier recovery; Clock recovery; Digital phase locked loop (DPLL); Dual loop DPLL; Fast acquisition; Fast locking; Gear shifting; Locking speed; Short preamble; Time recovery; Zero phase shift

Indexed keywords

ALGORITHMS; BANDWIDTH; DATA ACQUISITION; DATA COMMUNICATION SYSTEMS; PHASE SHIFT; SYNCHRONIZATION;

CARRIER RECOVERY; CLOCK RECOVERY; DUAL LOOP DIGITAL PHASE LOCKED LOOP (DPLL); GEAR SHIFTING ALGORITHMS; JITTER REDUCTION;

PHASE LOCKED LOOPS;

EID: 0031190631     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.598428     Document Type: Article

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