Design and Evaluation of Adiabatic Arithmetic Units

Analog Integrated Circuits and Signal Processing

Volumn 14, Issue 1-2, 1997, Pages 71-79

  Knapp, Micah C ^a,b,d,e,f   Kindlmann, Peter J ^a,f,g,h,i   Papaefthymiou, Marios C ^{a,c,f,j,k,l,m}  

^a Yale University   (United States)

^b HEWLETT PACKARD ENTERPRISE   (United States)

^c The Department of Civil and Environmental Engineering   (United States)

^d MOTOROLA INC   (United States)

^e BOSTON UNIVERSITY   (United States)

^f YALE UNIVERSITY   (United States)

^g Yale University ^*  (United States)

^h Yale's Instrumentation Lab   (United States)

ⁱ Yale and Congruent Design Inc   (United States)

^j UNIVERSITY OF MICHIGAN   (United States)

^k CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^l MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^m Univ Michigan's Adv Comp Arch L   (United States)

more..

Author keywords

Adders; Adiabatic design; Dynamic circuitry; Energy recovering circuitry; Low energy design; Multipliers

Indexed keywords

ADDERS; DESIGN; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; ELECTRIC INVERTERS; EVALUATION; MULTIPLYING CIRCUITS;

ARITHMETIC CIRCUITS;

VLSI CIRCUITS;

EID: 0031235547     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/978-1-4615-6101-9_7     Document Type: Article

References (10)

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