Inverse modeling of two-dimensional MOSFET dopant profile via capacitance of the source/drain gated diode

IEEE Transactions on Electron Devices

Volumn 47, Issue 7, 2000, Pages 1385-1392

  Chiang, C Y T ^b   Yeow, Y T ^a,b   Ghodsi, R ^a,c  

^a IEEE   (Australia)

^b UNIVERSITY OF QUEENSLAND   (Australia)

^c CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL REGION; DOPANT CONCENTRATION PROPILE; GATED DIODE; INVERSE MODELLING PROCESS;

CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; INVERSE PROBLEMS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SUBSTRATES; TWO DIMENSIONAL;

MOSFET DEVICES;

EID: 0034225559     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.848281     Document Type: Article

References (11)

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