Overlay performance of SR lithography in 64M DRAM layers

Microelectronic Engineering

Volumn 53, Issue 1, 2000, Pages 587-590

  Sumitani, H ^a   Suita, M ^a   Hifumi, T ^a   Watanabe, H ^a   Yabe, H ^b   Itoga, K ^b   Aya, S ^b   Marumoto, K ^a   Matsui, Y ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEPOSITION; DYNAMIC RANDOM ACCESS STORAGE; ETCHING; MASKS; SUBSTRATES; SYNCHROTRON RADIATION; X RAYS;

BIT LINE PATTERN; CANON X RAY STEPPER; STORAGE NODE CONTACT; SYNCHROTRON RADIATION LITHOGRAPHY;

X RAY LITHOGRAPHY;

EID: 0034205480     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00384-1     Document Type: Article

References (7)

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6. 6. S. Aya, et al., The 42nd Int. Conf. EIPBN Abstracts (1998) MK2.
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