Functional verification methodology of Chameleon processor

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 421-426

  Casaubieilh, Francoise ^a   McIsaac, Anthony ^a   Benjamin, Mike ^a   Bartley, Mike ^a   Pogodalla, Francois ^a   Rocheteau, Frederic ^a   Belhadj, Mohamed ^a   Eggleton, Jeremy ^a   Mas, Gerard ^a   Barrett, Geoff ^a   Berthet, Christian ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK SYNTHESIS; FORMAL LANGUAGES; FUNCTION EVALUATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

BLOCK DECOMPOSITION; CIRCUIT LEVEL VERIFICATION;

MICROPROCESSOR CHIPS;

EID: 0029723878     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240599     Document Type: Conference Paper

References (9)