Functional verification methodology for the PowerPC 604TM microprocessor

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 319-324

  Monaco, James ^a   Holloway, David ^a   Raina, Rajesh ^a  

^a Somerset Design Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

FUNCTIONAL LOGIC VERIFICATION; POWERPC 604 MICROPROCESSOR; SUPERSCALAR MICROPROCESSORS; VERILOG EVENT DRIVEN SIMULATOR;

MICROPROCESSOR CHIPS;

EID: 0029717582     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)