Estimation of maximum power for sequential circuits considering spurious transitions

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 746-751

  Wang, Chuan Yu ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; GATES (TRANSISTOR);

AUTOMATIC TEST GENERATION (ATG); SPURIOUS TRANSITIONS;

SEQUENTIAL CIRCUITS;

EID: 0031333385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)