Transport model in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memory applications

IEEE Transactions on Electron Devices

Volumn 47, Issue 2, 2000, Pages 372-377

  Irrera, Fernanda ^a   Marangelo, Luca ^a  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRON TRANSPORT PROPERTIES; ELECTRON TRAPS; ELECTRON TUNNELING; HOLE TRAPS; INTERFACES (MATERIALS); NONVOLATILE STORAGE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR STORAGE; SILICA;

FOWLER-NORDHEIM TUNNEL; POOLE-FRENKEL TUNNELING;

MOS CAPACITORS;

EID: 0033896237     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.822283     Document Type: Article

References (8)

1. S. Yokoyama, D. W. Dong, D. J. DiMaria, and S. K. Lai, "Characterization of plasma-enhanced chemically-vapor-deposited silicon-rich silicon dioxide/thermal silicon dioxide dual dielectric system," J. Appl. Phys.. vol. 54, p. 7058, 1983.
2. C. J. Lin et al., "Enhanced tunneling characteristics of PECVD Silicon Rich Oxide (SRO) for the application in low voltage flash EEPROM memories," IEEE Trans. Electron Devices, vol. 43, p. 2021, 1996.
3. 2 films and experimental application," J. Appl. Phys., vol. 51, p. 2722, 1980.
4. L. Dori, A. Acovic, J. D. DiMaria, and C. H. Hsu, "Optimized silicon rich oxide (SRO) deposition process for 5 V-only flash EEPROM applications," IEEE Trans. Electron Devices, vol. 14, p. 283, 1993.
5. K. T. Chang and K. Rose, "Enhanced injection at silicon-rich oxide interfaces," Appl. Phys. Lett., vol. 49, p. 868, 1986.
6. 2-SRO DEIS structures for EAROM's," IEEE Trans. Electron Devices, vol. 35, p. 1645, 1988.
7. 2/p-sub MOS capacitors for low-voltage nonvolatile memory applications. Experiment," IEEE Trans. Electron Devices, vol. 46, Nov. 1999.
8. D. Caputo, G. de Cesare, F. Irrera, and F. Palma, "Solar-blind UV photodetectors for large area applications," IEEE Trans. Electron Devices, vol.43, p. 1351, 1996.